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october 2007 rev 3 1/108 1 m58lt256jst m58lt256jsb 256 mbit (16 mb 16, multiple bank, multilevel, burst) 1.8 v supply, secure flash memories features supply voltage ?v dd = 1.7 v to 2.0 v for program, erase and read ?v ddq = 2.7 v to 3.6 v for i/o buffers ?v pp = 9 v for fast program synchronous/asynchronous read ? synchronous burst read mode: 52 mhz ? random access: 85 ns ? asynchronous page read mode synchronous burst read suspend programming time ? 5 s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 16 mbit banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block protection ? all blocks protected at power-up ? any combination of blocks can be protected with zero latency ? absolute write protection with v pp = v ss security ? software security features ? 64 bit unique device number ? 2112 bit user programmable otp cells cfi (common flash interface) 100 000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? top device codes: m58lt256jst: 885eh ? bottom device codes m58lt256jsb: 885fh tbga64 package ? ecopack? compliant tbga64 (za) 10 x 13 mm bga www.st.com
contents m58lt256jst, m58lt256jsb 2/108 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 address inputs (a0-a23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.9 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.14 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m58lt256jst, m58lt256jsb contents 3/108 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 the blank check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.10 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . 25 4.10.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10.2 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.10.3 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.13 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.14 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.15 block protect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.16 block unprotect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 erase/blank check status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.7 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.8 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . 36 6 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 x latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
contents m58lt256jst, m58lt256jsb 4/108 6.9 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.1 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 47 9 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1 reading a block?s protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2 protected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3 unprotected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.4 protection operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . 51 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 52 11 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 appendix c flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 appendix d command interface state ta bles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
m58lt256jst, m58lt256jsb list of tables 5/108 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. protection register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. x latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 12. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 14. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 15. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 16. program/erase times and endurance cycles , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 18. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 21. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 22. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 24. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 26. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 27. tbga64 10 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 29. m58lt256jst - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 30. m58lt256jst - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 31. m58lt256jst - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 32. m58lt256jsb - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 33. m58lt256jsb - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 34. m58lt256jsb - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 35. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 36. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 37. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 38. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 39. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 40. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 41. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 42. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 43. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 44. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 45. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 46. command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 101 table 47. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
list of tables m58lt256jst, m58lt256jsb 6/108 table 48. command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 105 table 49. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
m58lt256jst, m58lt256jsb list of figures 7/108 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. tbga64 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5. x latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 9. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 10. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 11. synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 12. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 13. synchronous burst read suspend ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 14. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 15. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 16. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 17. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 18. tbga64 10 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 19. program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 figure 20. blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 21. buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 22. program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 23. block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 24. erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 25. protect/unprotect operation flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 26. protection register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 27. buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . 97
description m58lt256jst, m58lt256jsb 8/108 1 description the m58lt256jst/b are 256 mbit (16 mbit x 16) non-volatile secure flash memories. they may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 v to 2.0 v v dd supply for the circuitry and a 2.7 v to 3.6 v v ddq supply for the input/output pins. an optional 9 v v pp power supply is provided to speed up factory programming. the devices feature an asymmetrical block architecture. the m58lt256jst/b have an array of 259 blocks, and are divided into 16 mbit banks. there are 15 banks each containing 16 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 15 main blocks of 64 kwords. the multiple bank architecture allows dual operations. while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in ta bl e 2 , and the memory map is shown in figure 3 . the parameter blocks are located at the top of the memory address space for the m58lt256jst, and at the bottom for the m58lt256jsb. each block can be erased separately. erase can be suspended to perform a program or read operation in any other block, and then resumed. program can be suspended to read data at any memory location except for the one being programmed, and then resumed. each block can be programmed and erased over 100 000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller manages the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array. at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at frequencies of up to 52 mhz. the synchronous burst read operation can be suspended and resumed. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. the m58lt256jst/b features an instant, individu al block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. they can be protected individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are protected at power-up.
m58lt256jst, m58lt256jsb description 9/108 the device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 otp (one-time-programmable) protection registers of 128 bits each. the first protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 64 bit segment otp by the user. the user programmable segment can be permanently protected. figure 4 , shows the protection register memory map. the m58lt256jst/b also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. for further information please contact stmicroelectronics. the m58lt256jst/b are offered in a tbga64, 10 13 mm, 1 mm pitch package, and are supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai13299 a0-a23 w dq0-dq15 v dd m58lt256jst m58lt256jsb e v ss 16 g rp v ddq v pp l k wait v ssq
description m58lt256jst, m58lt256jsb 10/108 table 1. signal names signal name function direction a0-a23 address inputs inputs dq0-dq15 data input/outputs, command inputs i/o e chip enable input g output enable input w write enable input rp reset input k clock input l latch enable input wait wait output v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally du do not use
m58lt256jst, m58lt256jsb description 11/108 figure 2. tbga64 package connections (top view through package) ai13414 dq6 a0 v ssq v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ss dq13 d a15 a19 e a8 c a16 a20 a10 a14 k a7 b a18 a1 a12 a13 a 8 7 6 5 4 3 2 1 a6 a2 a3 a4 g f e dq0 a5 v pp a17 a9 a11 rp dq15 dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss nc nc nc nc nc nc nc nc a23 a21 a22 wait nc nc l
description m58lt256jst, m58lt256jsb 12/108 figure 3. memory map table 2. bank architecture number bank size parameter blocks main blocks parameter bank 16 mbits 4 blocks of 16 kwords 15 blocks of 64 kwords bank 1 16 mbits - 16 blocks of 64 kwords bank 2 16 mbits - 16 blocks of 64 kwords bank 3 16 mbits - 16 blocks of 64 kwords ---- ---- ---- ---- bank 14 16 mbits - 16 blocks of 64 kwords bank 15 16 mbits - 16 blocks of 64 kwords ai13403b m58lt256jst - top boot block address lines a0-a23 16 main blocks bank 15 m58lt256jsb - bottom boot block address lines a0-a23 64 kword 000000h 00ffffh 64 kword 0f0000h 0fffffh 64 kword c00000h c0ffffh 64 kword cf0000h cfffffh 64 kword d00000h d0ffffh 64 kword df0000h dfffffh 64 kword e00000h e0ffffh 64 kword ef0000h efffffh 64 kword f00000h f0ffffh 64 kword fe0000h feffffh 16 kword ff0000h ff3fffh 16 kword ffc000h ffffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 1f0000h 1fffffh 64 kword 200000h 20ffffh 64 kword 2f0000h 2fffffh 64 kword 300000h 30ffffh 64 kword 3f0000h 3fffffh 64 kword f00000h f0ffffh 64 kword ff0000h ffffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 16 main blocks 16 main blocks 16 main blocks 15 main blocks 4 parameter blocks 15 main blocks 16 main blocks 16 main blocks 16 main blocks 16 main blocks
m58lt256jst, m58lt256jsb signal descriptions 13/108 2 signal descriptions see figure 1: logic diagram and table 1: signal names for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a23) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data input/output (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 output enable (g ) the output enable input controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable input controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first. 2.6 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 20: dc characteristics - currents for the value of i dd2. after reset all blocks are in the protected state and the configuration register is reset. when reset is at v ih , the device is in normal op eration. upon exiting reset mode the device enters asynchronous read mode, however, a negative transition of chip enable or latch enable is required to ensure valid data outputs.
signal descriptions m58lt256jst, m58lt256jsb 14/108 2.7 latch enable (l ) latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . 2.8 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.9 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih , output enable is at v ih or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. 2.10 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.11 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . 2.12 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0 v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives absolute protection against program or erase, while v pp in the v pp1 range enables these functions (see tables 20 and 21 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed.
m58lt256jst, m58lt256jsb signal descriptions 15/108 2.13 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.14 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1 f ceramic capacitor close to the pin (high-frequency, in herently-low inductance capacitors should be as close as possible to the package). see figure 8: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
bus operations m58lt256jst, m58lt256jsb 16/108 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby and reset. see table 3: bus operations for a summary. typically glitches of less than 5 ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see section 4: command interface ). see figures 9 , 10 and 11 read ac waveforms, and tables 22 and 23 read ac characteristics for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses must be latched prior to the write operation by toggling latch enable (when chip enable is at v il ). the latch enable must be tied to v ih during the bus write operation. see figures 15 and 16 , write ac waveforms, and tables 24 and 25 , write ac characteristics for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih .
m58lt256jst, m58lt256jsb bus operations 17/108 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level i dd3 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. 3.6 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the reset level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 3. bus operations (1) 1. x = ?don't care?. operation e g w l rp wait (2) 2. wait signal polarity is configured us ing the set configuration register command. dq15-dq0 bus read v il v il v ih v il (3) 3. l can be tied to v ih if the valid address has been previously latched. v ih data output bus write v il v ih v il v il (3) v ih data input address latch v il xv ih v il v ih data output or hi-z (4) 4. depends on g . output disable v il v ih v ih xv ih hi-z hi-z standby v ih xxxv ih hi-z hi-z reset xxxxv il hi-z hi-z
command interface m58lt256jst, m58lt256jsb 18/108 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller manages all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands are ignored. refer to table 4: command codes , table 5: standard commands , ta bl e 6 : fa c t o r y commands and appendix d: command interface state tables for a summary of the command interface. table 4. command codes hex code command 01h block protect confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 40h program setup 50h clear status register 60h block protect setup, block unprotect setup and set configuration register setup 70h read status register 80h buffer enhanced factory program setup 90h read electronic signature 98h read cfi query b0h program/erase suspend bch blank check setup c0h protection register program cbh blank check confirm d0h program/erase resume, block erase confir m, block unprotect confirm, buffer program or buffer enhanced factory program confirm e8h buffer program ffh read array
m58lt256jst, m58lt256jsb command interface 19/108 4.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command. once a bank is in read array mode, subsequent read operations output the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode. the program or erase operation continues, however, the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. 4.2 read status register command the device contains a status register that is used to monitor program or erase operations. the read status register command is used to read the contents of the status register for the addressed bank. one bus write cycle is required to issue the r ead status register command. once a bank is in read status register mode, subsequent read operations output the contents of the status register. the status register data is la tched on the falling edge of the ch ip enable or output enable signals. either chip enable or output enable must be toggled to update the status register data. the read status register command can be issued at any time, even during program or erase operations. the read status register command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the status register. a read array command is required to return the bank to read array mode. see ta bl e 9 for the description of the status register bits.
command interface m58lt256jst, m58lt256jsb 20/108 4.3 read electronic signature command the read electronic signature command reads the manufacturer and device codes, the protection status of the addressed bank, the protection register, and the configuration register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank outputs the manufacturer code, the device code, the protection status of the addressed bank, the protection register, or the configuration register (see ta bl e 8 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the parameter bank and the electronic signature location are not allowed (see table 15: dual operation limitations for details). if a read electronic signature command is issu ed to a bank that is executing a program or erase operation, the bank goes into read electronic signature mode. subsequent bus read cycles output the electronic signature data and the program/erase controller continues to program or erase in the background. the read electronic signature command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the electronic signature. a read array command is required to return the bank to read array mode. 4.4 read cfi query command the read cfi query command reads data from the cfi. one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank read from the common flash interface. the read cfi query command can be issued at any time, even during program or erase operations. if a read cfi query command is issued to a bank that is executing a program or erase operation, the bank goes into read cfi query mode. subsequent bus read cycles output the cfi data and the program/erase controller continues to program or erase in the background. the read cfi query command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read from the cfi. a read array command is required to return the bank to read array mode. dual operations between the parameter bank and the cfi memory space are not allowed (see table 15: dual operation limitations for details). see appendix b: common flash interface , tables 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 and 44 for details on the information contained in the common flash interface memory area.
m58lt256jst, m58lt256jsb command interface 21/108 4.5 clear status register command the clear status register command resets (set to ?0?) all error bits (sr1, 3, 4 and 5) in the status register. one bus write cycle is required to issue the clear status register command. the clear status register command does not affect the read mode of the bank. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command. 4.6 block erase command the block erase command erases a block. it sets all the bits within the selected block to ?1? and all previous data in the block is lost. if the block is protected, then the erase operation aborts, the data in the block is not changed, and the status register outputs the error. two bus write cycles are required to issue the command. the first bus cycle sets up the block erase command. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase confirm code, status register bits sr4 and sr5 are set, and the command is aborted. once the command is issued, the bank enters read status register mode and any read operation within the addressed bank outputs t he contents of the status register. a read array command is required to return the bank to read array mode. during block erase operations the bank containing the block being erased only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands, and all other commands are ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. refer to section 8 for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 16: program/erase times and endurance cycles, . see appendix c , figure 23: block erase flowchart and pseudocode for a suggested flowchart for using the block erase command.
command interface m58lt256jst, m58lt256jsb 22/108 4.7 the blank check command the blank check command checks whether a main array block has been completely erased. only one block at a time can be checked. to use the blank check command v pp must be equal to v pph . if v pp is not equal to v pph , the device ignores the command and no error is shown in the status register. two bus cycles are required to issue the blank check command: the first bus cycle writes the blank check command (bch) to any address in the block to be checked. the second bus cycle writes the blank check confirm command (cbh) to any address in the block to be checked and starts the blank check operation. if the second bus cycle is not blank check confirm, status register bits sr4 and sr5 are set to '1' and the command aborts. once the command is issued, the addressed bank automatically enters the status register mode and further reads within the bank output the status register contents. the only operation permitted during blank chec k is read status register. dual operations are not supported while a blank check operation is in progress. blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. the sr7 status register bit indicates the status of the blank check operation in progress. sr7 = '0' means that the blank check operation is still ongoing, and sr7 = '1' means that the operation is complete. the sr5 status register bit goes high (sr5 = '1') to indicate that the blank check operation has failed. at the end of the operation the bank remains in the read status register mode until another command is written to the command interface. see appendix c , figure 20: blank check flowchart and pseudocode for a suggested flowchart for using the blank check command. typical blank check times are given in table 16: program/erase times and endurance cycles, .
m58lt256jst, m58lt256jsb command interface 23/108 4.8 program command the program command is used to program a single word to the memory array. if the block being programmed is protected, then the program operation aborts, the data in the block is not changed, and the status register outputs the error. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and data to be programmed and starts the program/erase controller. once the programming has started, read operations in the bank being programmed output the status register content. during a program operation, the bank containing the word being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands, and all other commands are ignored. a read array command is required to return the bank to read array mode. refer to section 8 for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 16: program/erase times and endurance cycles, . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. see appendix c , figure 19: program flowchart and pseudocode for the flowchart for using the program command.
command interface m58lt256jst, m58lt256jsb 24/108 4.9 buffer program command the buffer program command uses the device?s 32-word write buffer to speed up programming. up to 32 words can be loaded into the write buffer. the buffer program command dramatically reduces in-system programming time compared to the standard non- buffered program command. four successive steps are required to issue the buffer program command. 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. after the first bus write cycle, read operations in the bank output the contents of the status register. status register bit sr7 should be read to check that the buffer is available (sr7 = 1). if the buffer is not available (sr7 = 0), re-issue the buffer program command to update the status register contents. 2. the second bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed. 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. optimum performance is obtained when the start address corresponds to a 32-word boundary. 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program operation must lie within the same block. invalid address combinations or failing to follow the correct sequence of bus write cycles sets an error in the status register and aborts the operation without affecting the data in the memory array. if the status register bits sr4 and sr5 are set to '1', the buffer program command is not accepted. clear the status register before re-issuing the command. if the block being programmed is protected, an error is set in the status register and the operation aborts without affecting the data in the memory array. during buffer program operations the bank being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands, and all other commands are ignored. refer to section 8 for detailed information about simultaneous operations allowed in banks not being programmed. see appendix c , figure 21: buffer program flowchart and pseudocode for a suggested flowchart on using the buffer program command.
m58lt256jst, m58lt256jsb command interface 25/108 4.10 buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. if the block being programmed is protected, then the program operation aborts, the data in the block is not changed, and the status register outputs the error. the use of the buffer enhanced factory program command requires the following operating conditions: v pp must be set to v pph v dd must be within operating range ambient temperature t a must be 30 c 10 c the targeted block must be unprotected the start address must be aligned with the start of a 32-word buffer boundary the address must remain the start address throughout programming. dual operations are not supported during the buffer enhanced factory program operation and the command cannot be suspended. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase. please refer to ta bl e 6 : fa c t o r y commands for detailed information. 4.10.1 setup phase the buffer enhanced factory program command requires two bus write cycles to initiate the command. the first bus write cycle sets up the buffer enhanced factory program command. the second bus write cycle confirms the command. after the confirm command is issued, read operations output the contents of the status register. the read status register command must not be issued or it is interpreted as data to program. the status register p/ec bit sr7 should be read to check that the p/ec is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program operation is terminated. see section 5: status register for details on the error.
command interface m58lt256jst, m58lt256jsb 26/108 4.10.2 program an d verify phase the program and verify phase requires 32 cycles to program the 32 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to program less than 32 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/ec is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/ec increments the address location.if any address is given that is not in the same block as the start address, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/ec is ready for the next word. 3. once the write buffer is full, the data is programmed sequentially to the memory array. after the program operation the device automatically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to determine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed. 4.10.3 exit phase status register p/ec bit sr7 set to ?1? indicates that the device has exited the buffer enhanced factory program operation and returned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see section 5: status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. typical program times are given in ta bl e 1 6 . see appendix c , figure 27: buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the buffer enhanced factory program command.
m58lt256jst, m58lt256jsb command interface 27/108 4.11 program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. the command can be addressed to any bank. the program/erase resume command is required to restart the suspended operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register are set to ?1?. the following commands are accepted during program/erase suspend: ? program/erase resume ? read array (data from erase-suspended block or program-suspended word is not valid) ? read status register ? read electronic signature ? read cfi query in addition, if the suspended operation is a block erase, then the following commands are also accepted: ? clear status register ? program (except in erase-suspended block) ? buffer program (except in erase suspended blocks) ? block protect ? block unprotect during an erase suspend the block being erased can be protected by issuing the block protect command. when the program/erase resume command is issued, the operation completes. it is possible to accumulate multiple suspend operations. for example, it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. if a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation completes. the program/erase suspend command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode, the bank remains in that mode and outputs the corresponding data. refer to section 8 for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c , figure 22: program suspend and resume flowchart and pseudocode , and figure 24: erase suspend and resume flowchart and pseudocode for flowcharts for using the program/erase suspend command.
command interface m58lt256jst, m58lt256jsb 28/108 4.12 program/erase resume command the program/erase resume command restarts the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command, and the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode, the bank remains in that mode and outputs the corresponding data. if a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation completes. see appendix c , figure 22: program suspend and resume flowchart and pseudocode , and figure 24: erase suspend and resume flowchart and pseudocode for flowcharts for using the program/erase resume command. 4.13 protection register program command the protection register program command programs the user otp segments of the protection register and the two protection register locks. the device features 16 otp segments of 128 bits and one otp segment of 64 bits, as shown in figure 4: protection register memory map . the segments are programmed one word at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two bus write cycles are required to issue the protection register program command. the first bus cycle sets up the pr otection register program command. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the program operation has started. attempting to program a previously protected protection register results in a status register error. the protection register program cannot be suspended. dual operations between the parameter bank and the protection register memory space are not allowed (see ta bl e 1 5 : dual operation limitations for details) the two protection register locks protect the otp segments from further modification. the protection of the otp segments is not reversible. refer to figure 4: protection register memory map and table 8: protection register locks for details on the lock bits. see appendix c , figure 26: protection register program flowchart and pseudocode for a flowchart for using the protection register program command.
m58lt256jst, m58lt256jsb command interface 29/108 4.14 set configuration register command the set configuration register command writes a new value to the configuration register. two bus write cycles are required to issue the set configuration register command. the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, that is a0 = cr0, a1 = cr1, ?, a15 = cr15. addresses a16-a23 are ignored. read operations output the array content after the set configuration register command is issued. the read electronic signature command is required to read the updated contents of the configuration register. 4.15 block protect command the block protect command protects a block and prevents program or erase operations from changing the data in it. all blocks are protected after power-up or reset. two bus write cycles are required to issue the block protect command. the first bus cycle sets up the block protect command. the second bus write cycle latches the block address and protects the block. once the command has been issued, subsequent bus read operations read the status register. the protection status can be monitored for each block using the read electronic signature command. refer to section 9: block protection for a detailed explanation. see appendix c , figure 25: protect/unprotect operation flowchart and pseudocode for a flowchart for using the block protect command. 4.16 block unprotect command the block unprotect command unprotects a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unprotect command. the first bus cycle sets up the block unprotect command. the second bus write cycle latches the block address and unprotects the block. once the command has been issued, subsequent bus read operations read the status register. the protection status can be monitored for each block using the read electronic signature command. refer to section 9: block protection for a detailed explanation and appendix c , figure 25: protect/unprotect operation flowchart and pseudocode for a flowchart for using the block unprotect command.
command interface m58lt256jst, m58lt256jsb 30/108 table 5. standard commands (1) 1. x = ?don't care?, wa = word address in targeted bank, rd = read data, srd = status register data, esd = electronic signature data, qd = query data, ba = block addre ss, bka = bank address, pd = program data, pra = protection register address, pr d = protection register data, crd = configuration register data. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) 2. must be same bank as in the first cyc le. the signature addresses are listed in table 7 . srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write x 50h block erase 2 write bka or ba (3) 3. any address within the bank can be used. 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd buffer program (4) 4. n+1 is the number of words to be programmed. n+4 write ba e8h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 pd n+1 write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block protect 2 write bka or ba (3) 60h write ba 01h block unprotect 2 write bka or ba (3) 60h write ba d0h
m58lt256jst, m58lt256jsb command interface 31/108 table 6. factory commands command phase cycles bus write operations (1) 1. wa = word address in targeted bank, bka = bank a ddress, pd = program data, ba = block address, x = ?don?t care?. 1st 2nd 3rd final -1 final add data add data add data add data add data blank check 2 ba bch ba cbh buffer enhanced factory program setup 2 bka or wa (2) 2. any address within the bank can be used. 80h wa 1 d0h program/ verify (3) 3. the program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (4) 4. wa 1 is the start address, not ba 1 = not block address of wa 1 . x table 7. electronic signature codes code address (h) data (h) manufacturer code bank address + 000 0020 device code top bank address + 001 885e (m58lt256jst) bottom bank address + 001 885f (m58lt256jsb) block protection protected block address + 002 0001 unprotected 0000 configuration register bank address + 005 cr (1) 1. cr = configuration register, prld = protection register lock data. protection register pr0 lock st factory default bank address + 080 0002 otp area permanently protected 0000 protection register pr0 bank address + 081 bank address + 084 unique device number bank address + 085 bank address + 088 otp area protection register pr1 through pr16 lock bank address + 089 prld (1) protection registers pr1-pr16 bank address + 08a bank address + 109 otp area
command interface m58lt256jst, m58lt256jsb 32/108 figure 4. protection register memory map ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp protection register lock 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
m58lt256jst, m58lt256jsb command interface 33/108 table 8. protection register locks lock description number address bits lock 1 80h bit 0 pre-programmed to protect unique device number, address 81h to 84h in pr0 bit 1 protects 64 bits of otp segment, address 85h to 88h in pr0 bits 2 to 15 reserved lock 2 89h bit 0 protects 128 bits of otp segment pr1 bit 1 protects 128 bits of otp segment pr2 bit 2 protects 128 bits of otp segment pr3 ---- ---- bit 13 protects 128 bits of otp segment pr14 bit 14 protects 128 bits of otp segment pr15 bit 15 protects 128 bits of otp segment pr16
status register m58lt256jst, m58lt256jsb 34/108 5 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register (refer to section 4.2 for more details). to output the contents, the status register is latched and updat ed on the falling edge of the chip e nable or output enable signals, and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank always read the status register during program and erase operations if no read array command has been issued. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. the bits in the status register are summarized in table 9: status register bits . refer to ta bl e 9 in conjunction with th e following sections. 5.1 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active. when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses, the bit is high. 5.2 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase c ontroller inactive). sr6 is set within the erase suspend latency time of the program/erase suspend command being issued, therefore, the memory may still complete th e operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
m58lt256jst, m58lt256jsb status register 35/108 5.3 erase/blank check status bit (sr5) the erase/blank check status bit identifies if there was an error during a block erase operation. when the erase/blank check status bit is high (set to ?1?), the program/erase controller has applied th e maximum number of pulses to the block and still failed to verify that it has erased correctly. the erase/blank check status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). the erase/blank check status bit also indicate s whether an error occurred during the blank check operation. if the data at one or more locations in the block where the blank check command has been issued is different from ffffh, sr5 is set to '1'. once set high, the erase/blank check status bit must be set low by a clear status register command or a hardware reset before a new erase command is issued, otherwise, the new command appears to fail. 5.4 program status bit (sr4) the program status bit is used to identify if there was an error during a program operation. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. once set high, the program status bit must be set low by a clear status register command or a hardware reset before a new program command is issued; otherwise, the new command appears to fail. 5.5 v pp status bit (sr3) the v pp status bit identifies an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage. when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued; otherwise, the new command appears to fail.
status register m58lt256jst, m58lt256jsb 36/108 5.6 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command being issued, therefor e, the memory may still comple te the operation rather than entering the suspend mode. when a program/erase resume command is issued, the program suspend status bit returns low. 5.7 block protection status bit (sr1) the block protection status bit i identifies if a program or block erase operation has tried to modify the contents of a protected block. when the block protection status bit is high (set to ?1?), a program or erase operation has been attempted on a protected block. once set high, the block protection status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued; otherwise, the new command appears to fail. 5.8 bank write/multiple word program status bit (sr0) the bank write status bit indicates whether the addressed bank is programming or erasing. in buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. the bank write status bit should only be considered valid when the program/erase controller status bit sr7 is low (set to ?0?). when both the program/erase controller status bi t and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase controller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in buffer enhanced factory program mode if the multiple word program status bit is low (set to ?0?), the device is ready for the next word. if the multiple word program status bit is high (set to ?1?), the device is not ready for the next word. for further details on how to use the status register, see the flowcharts and pseudocodes provided in appendix c .
m58lt256jst, m58lt256jsb status register 37/108 table 9. status register bits bit name type logic level (1) 1. logic level '1' is high, '0' is low. definition sr7 p/ec status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase/blank check status error '1' erase/blank check error '0' erase/blank check success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (buffer enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next buffer loading or is going to exit the befp mode '0' sr7 = ?1? the device has exited the befp mode sr7 = ?0? the device is ready for the next buffer loading
configuration register m58lt256jst, m58lt256jsb 38/108 6 configuration register the configuration register configures the type of bus access that the memory performs. refer to section 7 for details on read operations. the configuration register is set through the command interface using the set configuration register command. after a reset or power-up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in ta b l e 1 1 the bits specify the selection of the burst length, burst type, burst x latency and the read operation. refer to figures 5 and 6 for examples of synchronous burst configurations. 6.1 read select bit (cr15) the read select bit, cr15, switches between asynchronous and synchronous read operations. when the read select bit is set to ?1?, read operations are asynchronous. when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access. 6.2 x latency bits (cr13-cr11) the x latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. refer to figure 5: x latency and data output configuration example . for correct operation the x latency bits can only assume the values in table 11: configuration register . ta bl e 1 0 shows how to set the x latency parameter, taking into account the speed class of the device and the frequency used to read the flash memory in synchronous mode. table 10. x latency settings fmax t k min x latency min 30 mhz 33 ns 3 40 mhz 25 ns 4 52 mhz 19 ns 5
m58lt256jst, m58lt256jsb configuration register 39/108 6.3 wait polarity bit (cr10) the wait polarity bit sets the polarity of the wait signal used in synchronous burst read mode. during synchronous burst read mode the wait signal indicates whether the data output are valid or a wait state must be inserted. when the wait polarity bit is set to ?0?, the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high. 6.4 data output configuration bit (cr9) the data output configuration bit configures the output to remain valid for either one or two clock cycles during synchronous mode. when the data output configuration bit is ?0? the output data is valid for one clock cycle, and when it is ?1?, the output data is valid for two clock cycles. the data output configuration bit must be configured using the following condition: t k > t kqv + t qvk_cpu where t k is the clock period t qvk_cpu is the data setup time required by the system cpu t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cycles). refer to figure 5: x latency and data output configuration example . 6.5 wait configuration bit (cr8) the wait configuration bit controls the timing of the wait output pin, wait, in synchronous burst read mode. when wait is asserted, data is not valid, and when wait is de-asserted, data is valid. when the wait configuration bit is low (set to ?0?), the wait output pin is asserted during the wait state. when the wait configuration bit is high (set to ?1?), the wait output pin is asserted one data cycle before the wait state. 6.6 burst type bit (cr7) the burst type bit determines the sequence of addresses read during synchronous burst reads. the burst type bit is high (set to ?1?), as the memory outputs from sequential addresses only. see table 12: burst type definition for the sequence of addresses output from a given starting address in sequential mode.
configuration register m58lt256jst, m58lt256jsb 40/108 6.7 valid clock edge bit (cr6) the valid clock edge bit, cr6, configures the active edge of the clock, k, during synchronous read operations. when the valid cl ock edge bit is low (set to ?0?) the falling edge of the clock is the active edge. when the valid clock edge bit is high (set to ?1?) the rising edge of the clock is the active edge. 6.8 wrap burst bit (cr3) the wrap burst bit, cr3, selects between wrap and no wrap. synchronous burst reads can be confined inside the 4 or 8-word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is low (set to ?0?), the burst read wraps. when it is high (set to ?1?) the burst read does not wrap. 6.9 burst length bits (cr2-cr0) the burst length bits sets the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, in 4, 8 or 16-word no-wrap, depending on the starting address, the device asserts the wait signal to indicate that a delay is necessary before the data is output. if the starting address is aligned to an 8-word boundary, no wait state is needed and the wait output is not asserted. if the starting address is not aligned to an 8-word boundary, wait becomes asserted when the burst sequence crosses the first 8-word boundary to indicate that the device needs an internal delay to read the successive words in the array. wait is asserted only once during a continuous burst access. see also table 12: burst type definition . cr14, cr5 and cr4 are reserved for future use.
m58lt256jst, m58lt256jsb configuration register 41/108 table 11. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x latency 010 2 clock latency (1) 1. the combination x latency=2, data held for two clock cycles and wait active one data cycle before the wait state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) other configurations reserved cr10 wait polarity 0 wait is active low 1 wait is active high (default) cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) (1) cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (1) (default) cr7 burst type 0reserved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 111 continuous (default)
configuration register m58lt256jst, m58lt256jsb 42/108 table 12. burst type definition mode start add. sequential continuous burst 4 words 8 words 16 words wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 n/a 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12- 13... ... 12 12-13-14-15 12-13-14-15-8-9- 10-11 12-13-14-15-16- 17... 13 13-14-15-12 13-14-15-8-9-10- 11-12 13-14-15-16-17- 18... 14 14-15-12-13 14-15-8-9-10-11- 12-13 14-15-16-17-18- 19... 15 15-12-13-14 15-8-9-10-11-12- 13-14 15-16-17-18-19- 20... no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3 -4-5-6-7-8-9-10-11-12-13-14-15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5 -6-7-8--9-10-11-12-13-14-15-16 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5 --6-7-8-9-10-11-12-13-14-15-16-17 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6- 7-8-9-10-11-12-13-14-15-16-17-18 ... 7 7-8-9-10 7-8-9-10-11-12-13- 14 7-8-9-10-11-12-13-14 -15-16-17-18-19-20- 21-22 ... 12 12-13-14-15 12-13-14-15-16-17- 18-19 12-13-14-15-16-17-18- 19-20-21-22-23-24- 25-26-27 13 13-14-15-16 13-14-15-16-17-18- 19-20 13-14-15-16-17-18-19- 20-21-22-23-24-25- 26-27-28 14 14-15-16-17 14-15-16-17-18-19- 20-21 14-15-16-17-18-19-20- 21-22-23-24-25-26- 27-28-29 15 15-16-17-18 15-16-17-18-19-20- 21-22 15-16-17-18-19-20-21- 22-23-24-25-26-27- 28-29-30
m58lt256jst, m58lt256jsb configuration register 43/108 figure 5. x latency and data output configuration example 1. the settings shown are x latency = 4, data output held for one clock cycle. figure 6. wait configuration example ai08904 a23-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle e tdelay ai08905 a23-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
read modes m58lt256jst, m58lt256jsb 44/108 7 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous. if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see section 6: configuration register for details). all banks support both asynchronous and synchronous read operations. 7.1 asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, that is the memory array, status register, common flash interface or the electronic signature, depending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. asynchronous read operations can be performed in two different ways, asynchronous random access read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. in asynchronous read mode a page of data is internally read and stored in a page buffer. the page has a size of 8 words and is addressed by address inputs a0, a1 and a2. the first read operation within the page has a longer access time (t avqv , random access time), subsequent reads within the same page have much shorter access times (t avqv1 , page access time). if the page changes then the normal, longer timings apply again. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150 ns, the device au tomatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always de-asserted. see table 22: asynchronous read ac characteristics , figure 9: asynchronous random access read ac waveforms for details.
m58lt256jst, m58lt256jsb read modes 45/108 7.2 synchronous burst read mode in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode c an only be used to read the memory array. for other read operations, such as read status register, read cfi and read electronic signature, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence starts at the first clock ed ge (rising or falling depending on valid clock edge bit cr6 in the configurat ion register) after the falling ed ge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr13-cr11 of the configuration register. the number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output configuration bit cr9). the order of the data output can be modified through the wrap burst bit in the configuration register. the burst sequence is sequential and can be confined inside the 4 or 8-word boundary (wrap) or overcome the boundary (no wrap). the wait signal may be asserted to indicate to the system that an output delay is occurring. this delay depends on the starting address of the burst sequence and on the burst configuration. wait is asserted during the x latency, the wait state and at the end of a 4, 8 and 16-word burst. it is only de-asserted when output data is valid. in continuous burst read mode a wait state occurs when crossing the first 16-word boundary. if the starting address is aligned to the burst length (4, 8 or 16 words), the wrapped configuration has no impact on the output sequence. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 23: synchronous read ac characteristics and figure 11: synchronous burst read ac waveforms for details. 7.2.1 synchronous burst read suspend a synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. it can be suspended during the initial access latency time (before data is output) or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspended when chip enable, e , is low and the current address has been latched (on a latch enable rising edge or on a valid clock edge). the clock signal is then halted at v ih or at v il , and output enable, g , goes high. when output enable, g , becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped.
read modes m58lt256jst, m58lt256jsb 46/108 wait being gated by e , it remains active and does not revert to high impedance when g goes high. so if two or more devices are connected to the system?s ready signal, to prevent bus contention the wait signal of the m58lt256jst/b should not be directly connected to the system?s ready signal. wait reverts to high-impedance when chip enable, e , goes high. see table 23: synchronous read ac characteristics and figure 13: synchronous burst read suspend ac waveforms for details. 7.3 single synchronous read mode single synchronous read operations are similar to synchronous burst read operations, except that the memory outputs the same data to the end of the operation. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is asserted during the x latency and at the end of a 4, 8 and 16-word burst. it is only de-asserted when output data are valid. see table 23: synchronous read ac characteristics and figure 11: synchronous burst read ac waveforms for details.
m58lt256jst, m58lt256jsb dual operations and multiple bank architecture 47/108 8 dual operations and multiple bank architecture the multiple bank architecture of the m58lt256jst/b gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. also if the suspended operation is erase, then a program command can be issued to another block. this means the device can have one block in erase suspend mode, one programming, and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, read operations are possible at any moment in the m58lt256jst/b device. dual operations between the parameter bank and either of the cfi, the otp or the electronic signature memory space are not allowed. ta b l e 1 5 shows which dual operations are allowed or not between the cfi, the otp, the electronic signature locations and the memory array. ta bl e s 13 and 14 show the dual operations possible in other banks and in the same bank.
dual operations and multiple bank architecture m58lt256jst, m58lt256jsb 48/108 table 13. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program, buffer program block erase program /erase suspend program /erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended ye s ye s ye s ye s ? ? ? ye s erase suspended ye s ye s ye s ye s ye s ? ? ye s table 14. dual operations allowed in same bank status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program, buffer program block erase program /erase suspend program /erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming ? (1) 1. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. ye s ye s ye s ? ? ye s ? erasing ? (1) ye s ye s ye s ? ? ye s ? program suspended ye s (2) 2. not allowed in the block that is being eras ed or in the word that is being programmed. ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s (1) ?? yes
m58lt256jst, m58lt256jsb dual operations and multiple bank architecture 49/108 table 15. dual operation limitations current status commands allowed read cfi/otp / electronic signature read parameter blocks read main blocks located in parameter bank not located in parameter bank programming/erasing parameter blocks no no no yes programming/ erasing main blocks located in parameter bank ye s n o n o ye s not located in parameter bank ye s ye s ye s in different bank only programming otp no no no no
block protection m58lt256jst, m58lt256jsb 50/108 9 block protection the m58lt256jst/b features an instant, individu al block protection scheme that allows any block to be protected or unprotected with no latency. this protection scheme has two levels of protection. protect/unprotect - this first level allows software only control of block protection. v pp v pplk - this second level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to protected and unprotected. appendix c , figure 25 shows a flowchart for the protection operations. 9.1 reading a block?s protection status the protection status of every block can be read in the read electronic signature mode of the device. to enter this mode issue the read electronic signature command. subsequent reads at the address specified in ta bl e 7 output the protection status of that block. the protection status is represented by dq0. dq0 indicates the block protect/unprotect status, is set by the protect command, and cleared by the unprotect command. the following sections explain the operation of the protection system. 9.2 protected state the default status of all blocks on power-up or after a hardware reset is protected (state = 1). protected blocks are fully protected from program or erase operations. any program or erase operations attempted on a protected block return an error in the status register. the status of a protected block can be changed to unprotected using the appropriate software commands. an unprotected block can be protected by issuing the protect command. 9.3 unprotected state unprotected blocks (state = 0) can be programmed or erased. all unprotected blocks return to the protected state after a hardware reset or when the device is powered-down. the status of an unprotected block can be changed to protected using the appropriate software commands. a protected block can be unprotected by issuing the unprotect command.
m58lt256jst, m58lt256jsb block protection 51/108 9.4 protection operations during erase suspend changes to block protection status can be performed during an erase suspend by using the standard protection command sequences to unprotect or protect a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block protection during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next, write the desired protect command sequence to a block and the protection status is changed. after completing any desired protect, read, or program operations, resume the erase operation with the erase resume command. if a block is protected during an erase suspend of the same block, the erase operation completse when the erase is resumed. protecti on operations cannot be performed during a program suspend.
program and erase times and endurance cycles m58lt256jst, m58lt256jsb 52/108 10 program and erase times and endurance cycles the program and erase times and the number of program/erase cycles per block are shown in ta b l e 1 6 . exact erase times may change depending on the memory array condition. the best case is when all the bits in the block are at ?0? (pre-programmed). the worst case is when all the bits in the block are at ?1? (not pre-prog rammed). usually, the system overhead is negligible with respect to the erase time. in the m58lt256jst/b the maximum number of program/erase cycles depends on the v pp voltage supply used. table 16. program/erase times and endurance cycles (1), (2) parameter condition min typ typical after 100 kw/e cycles max unit v pp = v dd erase parameter block (16 kword) 0.4 1 2.5 s main block (64 kword) pre-programmed 1 3 4 s not pre-programmed 1.2 4 s program (3) single word word program 80 400 s buffer program 80 400 s buffer (32 words) (buffer program) 300 1200 s main block (64 kword) 600 ms suspend latency program 20 25 s erase 20 25 s program/erase cycles (per block) main blocks 100 000 cycles parameter blocks 100 000 cycles v pp = v pph erase parameter block (16 kword) 0.4 2.5 s main block (64 kword) 1 4 s program (3) single word word program 80 400 s buffer enhanced factory program (4) 5400s buffer (32 words) buffer program 180 1200 s buffer enhanced factory program 150 1000 s main block (64 kwords) buffer program 360 ms buffer enhanced factory program 300 ms bank (16 mbits) buffer program 5.8 s buffer enhanced factory program 4.8 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles blank check main blocks 2 ms parameter blocks 0.5 ms 1. t a = ?25 to 85 c; v dd = 1.7 v to 2 v; v ddq = 1.7 v to 3.6 v. 2. values are liable to change with t he external system-level overhead (command sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. this is an average value on the entire device.
m58lt256jst, m58lt256jsb maximum ratings 53/108 11 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 17. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?40 85 c t bias temperature under bias ?40 85 c t stg storage temperature ?65 125 c v io input or output voltage ?0.5 4.2 v v dd supply voltage ?0.2 2.5 v v ddq input/output supply voltage ?0.2 3.8 v v pp program voltage ?0.2 10 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
dc and ac parameters m58lt256jst, m58lt256jsb 54/108 12 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow are derived from tests performed under the measurement conditions summarized in table 18: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 7. ac measurement i/o waveform table 18. operating and ac measurement conditions parameter m58lt256jst/b units 85 min max v dd supply voltage 1.7 2.0 v v ddq supply voltage 2.7 3.6 v v pp supply voltage (factory environment) 8.5 9.5 v v pp supply voltage (application environment) ?0.4 v ddq + 0.4 v ambient operating temperature ?25 85 c load capacitance (c l )30pf input rise and fall times 5 ns input pulse voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai06161 v ddq 0v v ddq /2
m58lt256jst, m58lt256jsb dc and ac parameters 55/108 figure 8. ac measurement load circuit table 19. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0 v 6 8 pf c out output capacitance v out = 0 v 8 12 pf ai12842 v ddq c l c l includes jig capacitance 22k ? device under test 0.1f v dd 0.1f v ddq 22k ?
dc and ac parameters m58lt256jst, m58lt256jsb 56/108 table 20. dc characteristics - currents symbol parameter test condition typ max unit i li input leakage current 0 v v in v ddq 1 a i lo output leakage current 0 v v out v ddq 1 a i dd1 supply current asynchronous read (f=5 mhz) e = v il , g = v ih 13 15 ma supply current synchronous read (f=52 mhz) 4 word 16 19 ma 8 word 18 20 ma 16 word 22 25 ma continuous 23 27 ma i dd2 supply current (reset) rp = v ss 0.2 v 50 110 a i dd3 supply current (standby) e = v dd 0.2 v k = v ss 50 110 a i dd4 supply current (automatic standby) e = v il , g = v ih 50 110 a i dd5 (1) 1. sampled only, not 100% tested. supply current (program) v pp = v pph 35 50 ma v pp = v dd 35 50 ma supply current (erase) v pp = v pph 35 50 ma v pp = v dd 35 50 ma i dd6 (1), (2) 2. v dd dual operation current is the sum of read and program or erase currents. supply current (dual operations) program/erase in one bank, asynchronous read in another bank 48 65 ma program/erase in one bank, synchronous read (continuous f=52 mhz) in another bank 58 77 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2 v k = v ss 50 110 a i pp1 (1) v pp supply current (program) v pp = v pph 822ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 822ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
m58lt256jst, m58lt256jsb dc and ac parameters 57/108 table 21. dc characteristics - voltages symbol parameter test co ndition min typ max unit v il input low voltage 0 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage i oh = ?100 a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 2.7 3.3 3.6 v v pph v pp program voltage factory program, erase 8.5 9.0 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1 v
dc and ac parameters m58lt256jst, m58lt256jsb 58/108 figure 9. asynchronous random access read ac waveforms ai08906b tavav telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-a23 valid valid l (2) tellh tllqv tlllh tavlh tlhax taxqx wait (1) teltv tehtz hi-z hi-z tavqv tgltv tghtz notes: 1. write enable, w, is high, wait is active low. 2. latch enable, l, can be kept low (also at board level) when the latch enable function is not required or supporte d.
m58lt256jst, m58lt256jsb dc and ac parameters 59/108 figure 10. asynchronous page read ac waveforms ai08907b a3-a23 e g a0-a2 valid add. l dq0-dq15 valid add. valid add. valid address valid address valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv (1) note 1. wait is active low. valid address latch outputs enabled valid data standby hi-z tgltv valid add. valid add. valid add. valid add. valid data valid data valid data valid data valid data valid data valid data
dc and ac parameters m58lt256jst, m58lt256jsb 60/108 table 22. asynchronous read ac characteristics symbol alt parameter m58lt256jst/b unit 85 read timings t avav t rc address valid to next address valid min 85 ns t avqv t acc address valid to output valid (random) max 85 ns t avqv1 t pag e address valid to output valid (page) max 25 ns t axqx (1) 1. sampled only, not 100% tested. t oh address transition to output transition min 0 ns t eltv chip enable low to wait valid max 25 ns t elqv (2) 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . t ce chip enable low to output valid max 85 ns t elqx (1) t lz chip enable low to output transition min 0 ns t ehtz chip enable high to wait hi-z max 17 ns t ehqx (1) t oh chip enable high to output transition min 0 ns t ehqz (1) t hz chip enable high to output hi-z max 17 ns t glqv (2) t oe output enable low to output valid max 25 ns t glqx (1) t olz output enable low to output transition min 0 ns t gltv output enable low to wait valid max 17 ns t ghqx (1) t oh output enable high to output transition min 0 ns t ghqz (1) t df output enable high to output hi-z max 17 ns t ghtz output enable high to wait hi-z max 17 ns latch timings t avlh t avadvh address valid to latch enable high min 10 ns t ellh t eladvh chip enable low to latch enable high min 10 ns t lhax t advhax latch enable high to address transition min 9 ns t lllh t advladvh latch enable pulse width min 10 ns t llqv t advlqv latch enable low to output valid (random) max 85 ns
m58lt256jst, m58lt256jsb dc and ac parameters 61/108 figure 11. synchronous burst read ac waveforms ai13723 dq0-dq15 e g a0-a23 l wait k (4) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tkhtv tehqx tehqz tghqx tghqz tkhtx hi-z valid note 2 tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the activ e edge of k is the rising one. tehel tkhqv tkhqx tkhqv tkhqx hi-z tgltv
dc and ac parameters m58lt256jst, m58lt256jsb 62/108 figure 12. single synchronous read ac waveforms 1. the wait signal is configured to be active dur ing wait state. wait signal is active low. 2. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the active edge is the rising one. ai13400 e g a0-a23 l wait (1,2) k (2) valid address tglqv tavkh tllkh telkh hi-z telqx tkhqv tglqx tkhtv dq0-dq15 valid hi-z telqv tgltv tghtz
m58lt256jst, m58lt256jsb dc and ac parameters 63/108 figure 13. synchronous burst read suspend ac waveforms ai13724 dq0-dq15 e g a0-a23 l wait (2) k (4) valid valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax valid valid note 1 tehqx tehqz tghqx tghqz hi-z tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal , k, can be configured as the active edge. here, the active edge is the rising one. tglqx tehel tghqz tglqv note 3 hi-z tgltv tghtz tgltv
dc and ac parameters m58lt256jst, m58lt256jsb 64/108 figure 14. clock input ac waveform table 23. synchronous read ac characteristics (1) (2) 1. sampled only, not 100% tested. 2. for other timings please refer to table 22: asynchronous r ead ac characteristics . symbol alt parameter m58lt256jst/b unit 85 synchronous read timings t avkh t avclkh address valid to clock high min 9 ns t elkh t elclkh chip enable low to clock high min 9 ns t ehel chip enable pulse width (subsequent synchronous reads) min 20 ns t ehtz chip enable high to wait hi-z max 17 ns t khax t clkhax clock high to address transition min 10 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 17 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 3 ns t llkh t advlclkh latch enable low to clock high min 9 ns clock specifications t khkh t clk clock period (f=52 mhz) min 19 ns t khkl t klkh clock high to clock low clock low to clock high min 6 ns t f t r clock fall or rise time max 2 ns ai06981 tkhkh tf tr tkhkl tklkh
m58lt256jst, m58lt256jsb dc and ac parameters 65/108 figure 15. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-a23 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai13401 twhgl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhvpl telkv k twhll twhav
dc and ac parameters m58lt256jst, m58lt256jsb 66/108 table 24. write ac characteristics, write enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter m58lt256jst/b unit 85 write enable controlled timings t avav t wc address valid to next address valid min 85 ns t avlh address valid to latch enable high min 10 ns t avwh (3) address valid to write enable high min 50 ns t dvwh t ds data valid to write enable high min 50 ns t ellh chip enable low to latch enable high min 10 ns t elwl t cs chip enable low to write enable low min 0 ns t elqv chip enable low to output valid min 85 ns t elkv chip enable low to clock valid min 9 ns t ghwl output enable high to write enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 10 ns t whav (2) 2. meaningful only if l is always kept low. write enable high to address valid min 0 ns t whax (2) t ah write enable high to address transition min 0 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whel (3) 3. t whel and t whll have this value when reading in the target ed bank or when reading following a set configuration register command. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a set configuration register command. if the first read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel and t whll are 0 ns. write enable high to chip enable low min 25 ns t whgl write enable high to output enable low min 0 ns t whll (3) write enable high to latch enable low min 25 ns t whwl t wph write enable high to write enable low min 25 ns t wlwh t wp write enable low to write enable high min 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 ns t vphwh t vps v pp high to write enable high min 200 ns t whvpl write enable high to v pp low min 200 ns
m58lt256jst, m58lt256jsb dc and ac parameters 67/108 figure 16. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-a23 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai13402 tehgl twhel bank address valid address l tavlh tlllh tlhax tghel tehvpl telkv k tellh
dc and ac parameters m58lt256jst, m58lt256jsb 68/108 table 25. write ac characteristics, chip enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter m58lt256jst/b unit 85 chip enable controlled timings t avav t wc address valid to next address valid min 85 ns t aveh address valid to chip enable high min 50 ns t avlh address valid to latch enable high min 10 ns t dveh t ds data valid to chip enable high min 50 ns t ehax t ah chip enable high to address transition min 0 ns t ehdx t dh chip enable high to input transition min 0 ns t ehel t cph chip enable high to chip enable low min 25 ns t ehgl chip enable high to output enable low min 0 ns t ehwh t ch chip enable high to write enable high min 0 ns t elkv chip enable low to clock valid min 9 ns t eleh t cp chip enable low to chip enable high min 50 ns t ellh chip enable low to latch enable high min 10 ns t elqv chip enable low to output valid min 85 ns t ghel output enable high to chip enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 10 ns t whel (2) 2. t whel has this value when reading in the targeted bank or when reading following a set configuration register command. system designer s should take this into account and may insert a software no-op instruction to delay the first read in the same bank a fter issuing any command and to delay the first read to any address after issuing a set conf iguration register command. if the first read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel is 0 ns. write enable high to chip enable low min 25 ns t wlel t cs write enable low to chip enable low min 0 ns protection timings t ehvpl chip enable high to v pp low min 200 ns t qvvpl output (status register) valid to v pp low min 0 ns t vpheh t vps v pp high to chip enable high min 200 ns
m58lt256jst, m58lt256jsb dc and ac parameters 69/108 figure 17. reset and power-up ac waveforms ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll table 26. reset and power-up ac characteristics symbol parameter test condition 85 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 25 s during erase min 25 s read min 80 ns other conditions min 200 s t phwl t phel t phgl t phll reset high to write enable low, chip enable low, output enable low, latch enable low min 30 ns t plph (1),(2) rp pulse width min 50 ns t vdhph (3) supply voltages high to reset high min 150 s 1. the device reset is possible but not guaranteed if t plph < 50 ns. 2. sampled only, not 100% tested. 3. it is important to assert rp r to allow proper cpu initialization during power-up or reset.
package mechanical m58lt256jst, m58lt256jsb 70/108 13 package mechanical to meet environmental requirements, st offers these devices in ecopack? packages, which have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 18. tbga64 10 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline 1. drawing is not to scale. e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m58lt256jst, m58lt256jsb package mechanical 71/108 table 27. tbga64 10 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.800 0.0315 b 0.350 0.500 0.0138 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 ? ? 0.2756 ? ? ddd 0.100 0.0039 e 1.000 ? ? 0.0394 ? ? e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 ? ? 0.2756 ? ? fd 1.500 ? ? 0.0591 ? ? fe 3.000 ? ? 0.1181 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ?
part numbering m58lt256jst, m58lt256jsb 72/108 14 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 28. ordering information scheme example: m58lt256jst 8 za 6 e device type m58 architecture l = multilevel, multiple bank, burst mode operating voltage t = v dd = 1.7 v to 2.0 v, v ddq = 2.7 v to 3.6 v density 256 = 256 mbit ( 16) technology j = 90 nm technology, multilevel design security s = secure parameter location t = top boot b = bottom boot speed 8 = 85 ns package za = tbga64, 10 13 mm, 1 mm pitch temperature range 6 = ?40 to 85 c packing option e = ecopack? package, standard packing f = ecopack? package, tape and reel packing t = tape and reel packing blank = standard packing
m58lt256jst, m58lt256jsb block address tables 73/108 appendix a block address tables the following set of equations can be used to calculate a complete set of block addresses using the information contained in tables 29 to 34 . to calculate the block base address from the block number: first it is necessary to calculate the bank number and the block number offset. this can be achieved using the following formulas: bank_number = (block_number ? 3) / 16 block_number_offset = block_number ? 3 ? (bank_number x 16) if bank_number = 0, the block base address can be directly read from tables 29 and 32 (parameter bank block addresses) in the block number offset row. otherwise: block_base_address = bank_base_address + block_base_address_offset to calculate the bank number and the block number from the block base address: if the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from tables 29 and 32 (parameter bank block addresses), in the row that corresponds to the address given. otherwise, the block number can be calculated using the formulas below: for the top configuration (m58lt256jst): block_number = ((not address) / 2 16 ) + 3 for the bottom configuration (m58lt256jsb): block_number = (address / 2 16 ) + 3 for both configurations the bank number and the block number offset can be calculated using the following formulas: bank_number = (block_number ? 3) / 16 block_number_offset = block_number ? 3 ? (bank_number x 16)
block address tables m58lt256jst, m58lt256jsb 74/108 table 29. m58lt256jst - parameter bank block addresses block number size (kwords) address range 0 16 ffc000-ffffff 1 16 ff8000-ffbfff 2 16 ff4000-ff7fff 3 16 ff0000-ff3fff 4 64 fe0000-feffff 5 64 fd0000-fdffff 6 64 fc0000-fcffff 7 64 fb0000-fbffff 8 64 fa0000-faffff 9 64 f90000-f9ffff 10 64 f80000-f8ffff 11 64 f70000-f7ffff 12 64 f60000-f6ffff 13 64 f50000-f5ffff 14 64 f40000-f4ffff 15 64 f30000-f3ffff 16 64 f20000-f2ffff 17 64 f10000-f1ffff 18 64 f00000-f0ffff
m58lt256jst, m58lt256jsb block address tables 75/108 1. there are two bank regions: bank regi on 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). table 30. m58lt256jst - main bank base addresses bank number block numbers bank base address 1 19-34 e00000 2 35-50 d00000 3 51-66 c00000 4 67-82 b00000 5 83-98 a00000 6 99-114 900000 7 115-130 800000 8 131-146 700000 9 147-162 600000 10 163-178 500000 11 179-194 400000 12 195-210 300000 13 211-226 200000 14 227-242 100000 15 243-258 000000 table 31. m58lt256jst - block addresses in main banks block number offset block base address offset 0 0f0000 1 0e0000 2 0d0000 3 0c0000 4 0b0000 5 0a0000 6 090000 7 080000 8 070000 9 060000 10 050000 11 040000 12 030000 13 020000 14 010000 15 000000
block address tables m58lt256jst, m58lt256jsb 76/108 table 32. m58lt256jsb - parameter bank block addresses block number size (kwords) address range 18 64 0f0000-0fffff 17 64 0e0000-0effff 16 64 0d0000-0dffff 15 64 0c0000-0cffff 14 64 0b0000-0bffff 13 64 0a0000-0affff 12 64 090000-09ffff 11 64 080000-08ffff 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
m58lt256jst, m58lt256jsb block address tables 77/108 1. there are two bank regions : bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 33. m58lt256jsb - main bank base addresses bank number block numbers bank base address 15 243-258 f00000 14 227-242 e00000 13 211-226 d00000 12 195-210 c00000 11 179-194 b00000 10 163-178 a00000 9 147-162 900000 8 131-146 800000 7 115-130 700000 6 99-114 600000 5 83-98 500000 4 67-82 400000 3 51-66 300000 2 35-50 200000 1 19-34 100000 table 34. m58lt256jsb - block addresses in main banks block number offset block base address offset 15 0f0000 14 0e0000 13 0d0000 12 0c0000 11 0b0000 10 0a0000 9 090000 8 080000 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000
common flash interface m58lt256jst, m58lt256jsb 78/108 appendix b common flash interface the cfi (common flash interface) is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 and 44 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64-bit unique security number is written (see figure 4: protection register memory map ). this area can only be accessed in read mode by the final user. it is impossible to change the security number after it has been written by st. issue a read array command to return to read mode. 1. the flash memory display the cfi data structure w hen cfi query command is issued. in this table are listed the main sub-sections detailed in tables 36 , 37 , 38 and 39 . query data is always presented on the lowest order data outputs. table 35. query structure overview offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string command set id and algorithm data offset 01bh system interface information device timing and voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp
m58lt256jst, m58lt256jsb common flash interface 79/108 table 36. cfi query identification string offset sub-section name description value 000h 0020h manufacturer code st 001h 885eh 885fh device code m58lt256jst m58lt256jsb to p bottom 002h-00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0001h primary algorithm command set and control interface id code 16-bit id code defining a specific algorithm 014h 0000h 015h offset = p = 000ah address for primary algorithm extended query table (see ta bl e 3 9 ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h
common flash interface m58lt256jst, m58lt256jsb 80/108 table 37. cfi query system interface information offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7 v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2 v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5 v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5 v 01fh 0008h typical time-out per single byte/word program = 2 n s 256 s 020h 0009h typical time-out for buffer program = 2 n s 512 s 021h 000ah typical time-out per individual block erase = 2 n ms 1 s 022h 0000h typical time-out for full chip erase = 2 n ms na 023h 0001h maximum time-out for word program = 2 n times typical 512 s 024h 0001h maximum time-out for buffer program = 2 n times typical 1024 s 025h 0002h maximum time-out per individual block erase = 2 n times typical 4 s 026h 0000h maximum time-out for chip erase = 2 n times typical na
m58lt256jst, m58lt256jsb common flash interface 81/108 table 38. device geometry definition offset data description value 027h 0019h device size = 2 n in number of bytes 32 mbytes 028h 029h 0001h 0000h flash device interface code description x 16 async. 02ah 02bh 0006h 0000h maximum number of bytes in multi-byte program or page = 2 n 64 bytes 02ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 m58lt256jst 02dh 02eh 00feh 0000h erase block region 1 information number of identical-size erase blocks = 00feh+1 255 02fh 030h 0000h 0002h erase block region 1 information block size in region 1 = 0200h * 256 byte 128 kbytes 031h 032h 0003h 0000h erase block region 2 information number of identical-size erase blocks = 0003h+1 4 033h 034h 0080h 0000h erase block region 2 information block size in region 2 = 0080h * 256 byte 32 kbytes 035h 038h reserved reserved for future erase block region information na m58lt256jsb 02dh 02eh 0003h 0000h erase block region 1 information number of identical-size erase block = 0003h+1 4 02fh 030h 0080h 0000h erase block region 1 information block size in region 1 = 0080h * 256 bytes 32 kbytes 031h 032h 00feh 0000h erase block region 2 information number of identical-size erase block = 00feh+1 255 033h 034h 0000h 0002h erase block region 2 information block size in region 2 = 0200h * 256 bytes 128 kbytes 035h 038h reserved reserved for future erase block region information na
common flash interface m58lt256jst, m58lt256jsb 82/108 table 39. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h =10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0033h minor version number, ascii "3" (p+5)h = 10fh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported(1 = yes, 0 = no) bit 1 erase suspend supported(1 = yes, 0 = no) bit 2 program suspend supported(1 = yes, 0 = no) bit 3 legacy protect/unprotect supported(1 = yes, 0 = no) bit 4 queued erase supported(1 = yes, 0 = no) bit 5 instant individual block locking supported(1 = yes, 0 = no) bit 6 protection bits supported(1 = yes, 0 = no) bit 7 page mode read supported(1 = yes, 0 = no) bit 8 synchronous read supported(1 = yes, 0 = no) bit 9 simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional feat ures follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? ye s (p+a)h = 114h 0001h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register protect/unprotect bit active (1 = yes, 0 = no) bit 1 block protect status register lock-down bit active (1 = ye s , 0 = n o ) bit 15 to 2 reserved for future use; undefined bits are ?0? ye s no (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8 v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9 v
m58lt256jst, m58lt256jsb common flash interface 83/108 table 40. protection register information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection fi eld 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+ 11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16
common flash interface m58lt256jst, m58lt256jsb 84/108 table 41. burst read information offset data description value (p+1d)h = 127h 0004h page-mode read capability bits 0-7 n? such that 2 n hex value represents the number of read-page bytes. see offset 0028h for device word width to determine page-mode data output width. 16 bytes (p+1e)h = 128h 0004h number of synchronous mode read configuration fields that follow. 4 (p+1f)h = 129h 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 0028h for word width to determine the burst data output width. 4 (p+20)h = 12ah 0002h synchronous mode read capability configuration 2 8 (p-21)h = 12bh (p+22)h = 12ch 0003h 0007h synchronous mode read ca pability configuration 3 16 synchronous mode read ca pability configuration 4 cont.
m58lt256jst, m58lt256jsb common flash interface 85/108 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there are tw o bank regions, see tables 29 to 34 . table 42. bank and erase block region information m58lt256jst m58lt256jsb description offset data offset data (p+23)h = 12dh 02h (p+23)h = 12dh 02h number of bank regions within the device table 43. bank and erase block region 1 information m58lt256jst m58lt256jsb description offset data offset data (p+24)h = 12eh 0fh (p+24)h = 12eh 01h number of identical banks within bank region 1 (p+25)h = 12fh 00h (p+25)h = 12fh 00h (p+26)h = 130h 11h (p+26)h = 130h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+27)h = 131h 00h (p+27)h = 131h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h (p+28)h = 132h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 01h (p+29)h = 133h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) . (p+2a)h = 134h 0fh (p+2a)h = 134h 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = num ber of bytes in erase block region (p+2b)h = 135h 00h (p+2b)h = 135h 00h (p+2c)h = 136h 00h (p+2c)h = 136h 80h (p+2d)h = 137h 02h (p+2d)h = 137h 00h (p+2e)h = 138h 64h (p+2e)h = 138h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+2f)h = 139h 00h (p+2f)h = 139h 00h
common flash interface m58lt256jst, m58lt256jsb 86/108 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there are tw o bank regions, see tables 29 to 34 . 3. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. (p+30)h = 13ah 02h (p+30)h = 13ah 02h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+31)h = 13bh 03h (p+31)h = 13bh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+32)h = 13ch 0eh bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n 256 = number of bytes in erase block region (p+33)h = 13dh 00h (p+34)h = 13eh 00h (p+35)h = 13fh 02h (p+36)h = 140h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+37)h = 141h 00h (p+38)h = 142h 02h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+39)h = 143h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved table 43. bank and erase block region 1 information (continued) m58lt256jst m58lt256jsb description offset data offset data
m58lt256jst, m58lt256jsb common flash interface 87/108 table 44. bank and erase block region 2 information m58lt256jst m58lt256jsb description offset data offset data (p+32)h = 13ch 01h (p+3a)h = 144h 0fh number of identical banks within bank region 2 (p+33)h = 13dh 00h (p+3b)h = 145h 00h (p+34)h = 13eh 11h (p+3c)h = 146h 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+35)h = 13fh 00h (p+3d)h = 147h 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+36)h = 140h 00h (p+3e)h = 148h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+37)h = 141h 02h (p+3f)h = 149h 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+38)h = 142h 0eh (p+40)h = 14ah 0fh bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n 256 = number of bytes in erase block region (p+39)h = 143h 00h (p+41)h = 14bh 00h (p+3a)h = 144h 00h (p+42)h = 14ch 00h (p+3b)h = 145h 02h (p+43)h = 14dh 02h (p+3c)h = 146h 64h (p+44)h = 14eh 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+3d)h = 147h 00h (p+45)h = 14fh 00h (p+3e)h = 148h 02h (p+46)h = 150h 02h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+3f)h = 149h 03h (p+47)h = 151h 03h bank region 2 (erase block type 1): page mode and synchronous mode capabilities (defined in ta b l e 4 1 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
common flash interface m58lt256jst, m58lt256jsb 88/108 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there are tw o bank regions, see tables 29 to 34 . 3. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. (p+40)h = 14ah 03h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n 256 = number of bytes in erase block region (p+41)h = 14bh 00h (p+42)h = 14ch 80h (p+43)h = 14dh 00h (p+44)h = 14eh 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+45)h = 14fh 00h (p+46)h = 150h 02h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+47)h = 151h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in ta b l e 4 1 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+48)h = 152h (p+48)h = 152h feature space definitions (p+49)h = 153h (p+43)h = 153h reserved table 44. bank and erase block region 2 information (continued) m58lt256jst m58lt256jsb description offset data offset data
m58lt256jst, m58lt256jsb flowcharts and pseudocodes 89/108 appendix c flowcharts and pseudocodes figure 19. program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudocodes m58lt256jst, m58lt256jsb 90/108 figure 20. blank check flowchart and pseudocode 1. any address within the bank can equally be used. 2. if an error is found, the status register must be cleared before further program/erase operations. write block address & bch start sr7 = 1 write block address & cbh read status register (1) sr4 = 1 sr5 = 1 sr5 = 0 no yes command sequence error (2) yes blank check error (2) no end blank_check_command (blocktocheck) { writetoflash (blocktocheck, 0xbc); writetoflash (blocktocheck, 0xcb); /* memory enters read status state after the blank check command */ do { status_register = readflash (blocktocheck); /* see note (1) */ /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr4==1) && (status_register.sr5==1) /* command sequence error */ error_handler () ; if (status_register.sr5==1) /* blank check error */ error_handler () ; } ai10520c
m58lt256jst, m58lt256jsb flowcharts and pseudocodes 91/108 figure 21. buffer program flowchart and pseudocode 1. n + 1 is the number of data being programmed. 2. next program data is an element belonging to buffer_progr am[].data; next program address is an element belonging to buffer_program[].address 3. routine for error check by reading sr3, sr4 and sr1. buffer program e8h command, start address ai08913b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) read status register no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /* buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { do {writetoflash ( start _address, 0xe8) ; status_register=readflash ( start _address); } while (status_register.sr7==0); writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x flowcharts and pseudocodes m58lt256jst, m58lt256jsb 92/108 figure 22. program suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be issu ed just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
m58lt256jst, m58lt256jsb flowcharts and pseudocodes 93/108 figure 23. block erase flowchart and pseudocode 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 20h (2) ai10976 start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
flowcharts and pseudocodes m58lt256jst, m58lt256jsb 94/108 figure 24. erase suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be is sued just before or just after the erase resume command. write 70h ai12897b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block or program or block protect/unprotect start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another block*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
m58lt256jst, m58lt256jsb flowcharts and pseudocodes 95/108 figure 25. protect/unprotect operation flowchart and pseudocode 1. any address within the bank can equally be used. write 01h, d0h ai12895 read block protect state yes no protection change confirmed? start write 60h (1) protect_operation_command (address, protect_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = protection_state_expected) error_handler () ; /*check the protection state (see read block signature table )* / writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (protect_operation==protect) /*to protect the block*/ writetoflash (address, 0x01) ; else if (protect_operation==unprotect) /*to unprotect the block*/ writetoflash (address, 0xd0) ; writetoflash (address, 0x90) ; /*see note (1) */
flowcharts and pseudocodes m58lt256jst, m58lt256jsb 96/108 figure 26. protection register program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58lt256jst, m58lt256jsb flowcharts and pseudocodes 97/108 figure 27. buffer enhanced factory program flowchart and pseudocode write 80h to address wa1 ai12898 start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes sr4 = 1 no no no no setup phase program and verify phase exit phase buffer_enhanced_factory_program_command (start_address, dataflow[]) { writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do { do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) error_handler ( ) ;/*v pp error */ if (status_register.sr1==1) error_handler ( ) ;/* protected block */ } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<32) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); }
command interface state tables m58lt256jst, m58lt256jsb 98/108 appendix d command interface state tables table 45. command interface states - modify table, next state (1) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unprotect confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h) ready ready program setup bp setup erase setup befp setup blank check setup ready protect/cr setup ready (protect error) ready (unprotect block) ready (protect error) otp setup otp busy busy otp busy is in otp busy otp busy is in otp busy otp busy is in otp busy otp busy program setup program busy busy program busy is in program busy program busy is in program busy program busy program suspend program busy is in program busy program busy suspend ps is in ps ps is in program suspend ps program busy program suspend is in ps program suspend buffer program setup buffer program load 1 (give word count load (n-1)); buffer load 1 if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 (data load) buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) bp busy ready (error) busy bp busy is in bp busy bp busy is in bp busy bp busy bp suspend buffer program busy is in bp busy buffer program busy suspend bp suspend is in bp suspend bp suspend is in bp suspend bp suspend bp busy buffer program suspend is in bp suspend buffer program suspend
m58lt256jst, m58lt256jsb command interface state tables 99/108 erase setup ready (error) erase busy ready (error) busy erase busy is in erase busy erase busy is in erase busy erase busy erase suspend erase busy is in erase busy erase busy suspend erase suspend program in es bp in es is in erase suspend es erase busy erase suspend is in es erase suspend program in erase suspend setup program busy in erase suspend busy program busy in es is in program busy in es program busy in es is in program busy in es program busy in es ps in es program busy in erase suspend is in program busy in es program busy in erase suspend suspend ps in es is in ps in es ps in es is in program suspend in es ps in es program busy in es program suspend in erase suspend is in ps in es program suspend in erase suspend buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)); if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 buffer load 1 buffer program load 2 in erase suspend (data load) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm erase suspend (sequence error) bp busy in es erase suspend (sequence error) busy bp busy in es is in bp busy in es bp busy in es is in bp busy in es bp busy in es bp suspend in es buffer program busy in es is in bp busy in es buffer program busy in erase suspend suspend bp suspend in es is in bp suspend in es bp suspend in es is in bp suspend in erase suspend bp suspend in es bp busy in erase suspend buffer program suspend in erase suspend is in bp suspend in es bp suspend in erase suspend table 45. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unprotect confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h)
command interface state tables m58lt256jst, m58lt256jsb 100/108 blank check setup ready (error) blank check busy ready (error) busy blank check busy protect/cr setup in erase suspend erase suspend (protect error) erase suspend erase suspend (protect error) buffer efp setup ready (error) befp busy ready (error) busy befp busy (6) 1. ci = command interface, cr = configuration register, bef p = buffer enhanced factory program, p/e c = program/erase controller, is = illegal state, bp = buffer program, es = erase suspend. 2. at power-up, all banks are in. issuing a read array co mmand to a busy bank, results in undetermined data output. 3. the two cycle command should be issued to the same bank address. 4. if the p/e c is active, both cycles are ignored. 5. the clear status register command clears the sr erro r bits except when the p/e c. is busy or suspended. 6. befp is allowed only when status register bi t sr0 is reset to '0'. befp is busy if block address is first befp address. any other commands are treated as data. table 45. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unprotect confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h)
m58lt256jst, m58lt256jsb command interface state tables 101/108 table 46. command interface states - modify table, next output state (1) (2) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4) (5) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unprotect confirm, befp confirm (4)(5) (d0h) blank check confirm (cbh) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup otp setup program setup in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend blank check setup protect/cr setup protect/cr setup in erase suspend
command interface state tables m58lt256jst, m58lt256jsb 102/108 otp busy array status register output unchanged status register output unchang ed status register ready electronic signature/ cfi program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend blank check busy illegal state output unchanged 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 3. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 4. the two cycle command should be issued to the same bank address. 5. if the p/ec is active, both cycles are ignored. table 46. command interface states - modify table, next output state (1) (2) (continued) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4) (5) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unprotect confirm, befp confirm (4)(5) (d0h) blank check confirm (cbh) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h)
m58lt256jst, m58lt256jsb command interface state tables 103/108 table 47. command interface states - lock table, next state (1) current ci state command input protect/cr setup (2) (60h) otp setup (2) (c0h) block protect confirm (01h) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) p/e c operation completed (5) ready protect/cr setup otp setup ready n/a protect/cr setup ready (protect error) ready ready (protect error) n/a otp setup otp busy n/a busy is in otp busy otp busy ready is in otp busy otp busy is ready program setup program busy n/a busy is in program busy program busy ready is in program busy program busy is ready suspend is in ps program suspend n/a is in ps program suspend buffer program setup buffer program load 1 (give word count load (n-1)); n/a buffer load 1 buffer program load 2 (6) exit see note (6) n/a buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) n/a confirm ready (error) n/a busy is in bp busy buffer program busy ready is in buffer program busy buffer program busy is ready suspend is in bp suspend buffer program suspend n/a is in bp suspend buffer program suspend erase setup ready (error) n/a busy is in erase busy erase busy ready is in erase busy erase busy is ready suspend protect/cr setup in es is in es erase suspend n/a is in es erase suspend
command interface state tables m58lt256jst, m58lt256jsb 104/108 program in erase suspend setup program busy in erase suspend n/a busy is in program busy in es program busy in erase suspend es is in program busy in es program busy in erase suspend is in es suspend is in ps in es program suspend in erase suspend n/a is in ps in es program suspend in erase suspend buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)) n/a buffer load 1 buffer program load 2 in erase suspend (7) exit see note (7) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm erase suspend (sequence error) busy is in bp busy in es buffer program busy in erase suspend es is in bp busy in es bp busy in es is in es suspend is in bp suspend in es buffer program suspend in erase suspend n/a is in bp suspend in es buffer program suspend in erase suspend blank check setup ready (error) n/a blank check busy blank check busy ready protect/cr setup in es erase suspend (protect error) erase suspend erase suspend (protect error) n/a befp setup ready (error) n/a busy befp busy (8) exit befp busy (8) n/a 1. ci = command interface, cr = configuration register, bef p = buffer enhanced factory program, p/e c = program/erase controller, is = illegal state, bp = buffer program, es = erase suspend, wa0 = address in a bl ock different from first befp address. 2. if the p/e c is active, both cycle are ignored. 3. befp exit when block address is different from first block address and data are ffffh. 4. illegal commands are those not defined in the command set. 5. n/a: not available. in this case the state remains unchanged. 6. if n=0 go to buffer program confirm. else (not =0) go to buffer program load 2 (data load) 7. if n=0 go to buffer program confirm in erase suspend. else (not =0) go to buffer program load 2 in erase suspend. 8. befp is allowed only when status register bit sr0 is set to '0'. befp is busy if block addr ess is first befp address. any other commands are treated as data. table 47. command interface states - lock table, next state (1) (continued) current ci state command input protect/cr setup (2) (60h) otp setup (2) (c0h) block protect confirm (01h) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) p/e c operation completed (5)
m58lt256jst, m58lt256jsb command interface state tables 105/108 table 48. command interface states - lock table, next output state (1) (2) current ci state command input protect/cr setup (3) (6 0h) blank check setup (bch) otp setup (3) (c0h) blank check confirm (cbh) block protect confirm (01h) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) p. e./c. operation completed program setup status register output unchanged erase setup otp setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend blank check setup protect/cr setup status register array status register protect/cr setup in erase suspend
command interface state tables m58lt256jst, m58lt256jsb 106/108 otp busy status register output unchanged array output unchanged ready program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend blank check busy illegal state output unchanged 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank's output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 3. if the p/ec is active, both cycles are ignored. 4. befp exit when block address is different from first block address and data are ffffh. 5. illegal commands are those not defined in the command set. table 48. command interface states - lock table, next output state (continued) (1) (2) current ci state command input protect/cr setup (3) (6 0h) blank check setup (bch) otp setup (3) (c0h) blank check confirm (cbh) block protect confirm (01h) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) p. e./c. operation completed
m58lt256jst, m58lt256jsb revision history 107/108 15 revision history table 49. document revision history date revision changes 18-jul-2006 0.1 initial release. 31-oct-2006 0.2 description of cr2-cr0 011 value modified in ta b l e 1 1 : configuration register and note 2 added. table 12: burst type definition modified. timings modified in table 16: program/erase times and endurance cycles, . v io max and v ddq max modified in table 17: absolute maximum ratings . values changed in table 20: dc characteristics - currents . v pp1 modified in table 21: dc characteristics - voltages . figure 24: erase suspend and resume flowchart and pseudocode modified. appendix d: command interface state tables modified. 18-dec-2006 0.3 document status promot ed from target specification to preliminary data. small text changes. wait (wait) signal behavior in relation to output enable modified. section 5.4: program status bit (sr4) and section 6.9: burst length bits (cr2-cr0) modified. device architecture corrected (see table 2: bank architecture , figure 3: memory map and appendix a: block address tables ). i dd1 and i dd6 parameter values updated in ta bl e 2 0 : d c characteristics - currents . figure 13: synchronous burst read suspend ac waveforms modified. t plwl , t plel , t plgl and t plll values modified under other conditions (see table 26: reset and power-up ac characteristics ). t eltv timing removed from figure 11: synchronous burst read ac waveforms , figure 13: synchronous burst read suspend ac waveforms and table 23: synchronous read ac characteristics . t eltv timing modified in table 22: asynchronous read ac characteristics . appendix b: common flash interface modified. 23-feb-2007 1 block lock down confirm (2fh) removed from table 47: command interface states - lock table, next state and table 48: command interface states - lock table, next output state . small text changes. 27-jun-2007 2 document status promot ed from preliminary data to full datasheet. section 7.2: synchronous burst read mode modified. 16 word boundary (wrap) feature removed from the document. two packing options added in table 28: ordering information scheme . small text changes. 01-oct-2007 3 changed deassertion condition in section 7.2: synchronous burst read mode to state that wait is only de-asserted when output data is valid. changed t a and t bias minimum values in ta b l e 1 7 : absolute maximum ratings from -25 to -40.
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